View MAX3670_295212.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2166; Rev 0; 9/01
Low-Jitter 155MHz/622MHz Clock Generator
General Description
The MAX3670 is a low-jitter 155MHz/622MHz reference clock generator IC designed for system clock distribution and frequency synchronization in OC-48 and OC-192 SONET/SDH and WDM transmission systems. The MAX3670 integrates a phase/frequency detector, an operational amplifier (op amp), prescaler dividers and input/output buffers. Using an external VCO, the MAX3670 can be configured easily as a phase-lock loop with bandwidth programmable from 15Hz to 20kHz. The MAX3670 operates from a single +3.3V or +5.0V supply, and dissipates 150mW (typ) at 3.3V. The operating temperature range is from -40C to +85C. The chip is available in a 5mm 5mm, 32-pin QFN package. o Single +3.3V or +5.0V Supply o Power Dissipation: 150mW at +3.3V Supply o External VCO Center Frequencies (fVCO): 155MHz to 670MHz o Reference Clock Frequencies: fVCO, fVCO/2, fVCO/8 o Main Clock Output Frequency: fVCO o Optional Output Clock Frequencies: fVCO, fVCO/2, fVCO/4, fVCO/8 o Low Intrinsic Jitter: <0.4psRMS o Loss-of-Lock Indicator o PECL Clock Output Interface
Features
MAX3670
Applications
OC-12 to OC-192 SONET/WDM Transport Systems Clock Jitter Clean-Up and Frequency Synchronization Frequency Conversion System Clock Distribution
Ordering Information
PART MAX3670EGJ TEMP. RANGE PIN-PACKAGE -40C to +85C 32 QFN-EP* (5mm x 5mm)
*Exposed pad Pin Configuration appears at end of data sheet.
Typical Application Circuit
3.3V 155MHz REFCLK+ REFCLK3.3V 142 VCCD MOUT+ MOUT142 142 VCOIN+ VCO KVCO = 25kHz/V 155MHz RSEL 100 VCOIN142 VSEL N.C. N.C. MAX3892 16:1 SERIALIZER
MAX3670
332 VC 0.01F 4700pF 500k OPAMPOPAMP+ 4700pF 500k POLAR GND
GSEL1 GSEL2 GSEL3
N.C.
3.3V SETUP FOR 10kHz LOOP BANDWIDTH
REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Jitter 155MHz/622MHz Clock Generator MAX3670
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .........................................................-0.5V to +7V Voltage at C2+, C2-, THADJ, CTH, GSEL1, GSEL2, GSEL3, LOL, RSEL, REFCLK-, REFCLK+, VSEL, VCOIN+, VCOIN-, VC, POLAR, PSEL1, PSEL2, COMP, OPAMP+, OPAMP- ..................................-0.5V to (VCC + 0.5V) PECL Output Current (MOUT+, MOUT-, POUT+, POUT-).................................................56mA Operating Temperature Range ...........................-40C to +85C Storage Temperature Range. ............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.3V 10% or VCC = +5.0V 10%, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Current SYMBOL ICC (Note 2) CONDITIONS MIN TYP 48 MAX 72 UNITS mA
INPUT SPECIFICATIONS (REFCLK, VCOIN) Input High Voltage Input Low Voltage VIH VIL VCC 1.16 VCC 1.81 VCC 1.3 7.5 12.8 AC-coupled 300 VCC 1.025 VCC 1.085 VCC 1.81 VCC 1.83 2.4 11.5 21.0 17.5 32.5 1900 VCC 0.88 V -40C to 0C 0C to +85C Output Low Voltage VOL -40C to 0C TTL SPECIFICATIONS Output High Voltage Output Low Voltage VOH VOL Sourcing 20A Sinking 2mA VCC 0.4 V V VCC 0.88 VCC 1.62 VCC 1.556 V VCC 0.88 VCC 1.48 V V
Input Bias Voltage Common-Mode Input Resistance Differential Input Resistance Differential Input Voltage Swing PECL OUTPUT SPECIFICATIONS 0C to +85C Output High Voltage VOH
V k k mVp-p
2
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.3V 10% or VCC = +5.0V 10%, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX VCC 0.3 VCC 0.5 3 90 High gain Low gain High gain Low gain 16 4 20 5 24.4 6.2 0.80 1.08 V UNITS
MAX3670
OPERATIONAL AMPLIFIER SPECIFICATIONS (Note 3) VCC = +3.3V 10% Op Amp Output Voltage Range VO VCC = +5.0V 10% Op Amp Input Offset Voltage Op Amp Open-Loop Gain Full-Scale PFD/CP Output Current PFD/CP Offset Current | VOS | AOL 0.5 0.3
mV dB
PHASE FREQUENCY DETECTOR (PFD)/CHARGE-PUMP (CP) SPECIFICATIONS (Note 4) | IPD | A % | IPD |
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.3V 10% or VCC = +5.0V 10%, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER Clock Output Frequency Optional Clock Output Frequency Clock Output Rise/Fall Time Clock Output Duty Cycle NOISE SPECIFICATIONS Random Noise Voltage at LoopFilter Output Spurious Noise Voltage at LoopFilter Output Power-Supply Rejection at LoopFilter Output PSR VNOISE Freq > 1kHz (Note 7) (Note 8) (Note 9) 30 50 1.14 VRMS /Hz VRMS dB fVCO = 622MHz fVCO = 155MHz Measured from 20% to 80% (Note 6) 45 622/311/ 155/78 155/78/ 38/19 280 55 SYMBOL CONDITIONS MIN TYP MAX 670 UNITS MHz
CLOCK OUTPUT SPECIFICATIONS
MHz
ps %
REFERENCE CLOCK INPUT SPECIFICATIONS Reference Clock Frequency Reference Clock Duty Cycle 30 622/ 155/78 670 70 MHz %
_______________________________________________________________________________________
3
Low-Jitter 155MHz/622MHz Clock Generator MAX3670
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.3V 10% or VCC = +5.0V 10%, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER PLL SPECIFICATIONS PLL Jitter Transfer Bandwidth Jitter Transfer Function OP AMP SPECIFICATION Unity-Gain Bandwidth VCO INPUT SPECIFICATION VCO Input Frequency VCO Input Slew Rate fVCO 0.5 622/155 670 MHz V/ns 7 MHz BW (Note 10) FJITTER BW (Note 11) 15 20,000 0.1 Hz dB SYMBOL CONDITIONS MIN TYP MAX UNITS
Specifications at -40C are guaranteed by design and characterization. Measured with PECL outputs unterminated. OPAMP specifications met with 10k load to ground or 5k load to VCC (POLAR = 0 and POLAR = VCC). PFD/CP currents are measured from pins OPAMP+ to OPAMP-. See Table 3 for gain settings. AC characteristics are guaranteed by design and characterization. Measured with 50% VCO input duty cycle. Random noise voltage at op amp output with 800k resistor connected between VC and OPAMP-, PFD/CP gain (KPD) = 5A/UI, and POLAR = 0. Measured with the PLL open loop and no REFCLK or VCO input. Note 8: Spurious noise voltage due to PFD/CP output pulses measured at op amp output with R1 = 800k, KPD = 5A/UI, and compare frequency 400 times greater than the higher-order pole frequency (see Design Procedure). Note 9: PSR measured with a 100mVp-p sine wave on VCC in a frequency range from 100Hz to 2MHz. External resistors R1 matched to within 1%, external capacitors C1 matched to within 10%. Measured closed loop with PLL bandwidth set to 200Hz. Note 10: The PLL 3dB bandwidth is adjusted from 15Hz to 20kHz by changing external components R1 and C1, by selecting the internal programmable divider ratio and phase-detector gain. Measured with VCO gain of 220ppm/V and C1 limited to 2.2F. Note 11: Measured at BW = 20kHz. When input jitter frequency is above PLL transfer bandwidth (BW), the jitter transfer function rolls off at -20dB/decade. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
4
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
MAX3670
SUPPLY CURRENT vs. TEMPERATURE
MAX3670 toc01
EDGE SPEED vs. TEMPERATURE
280 270 260 250 240 230 220 210 200 190 180 170 160 150 -40
MAX3670 toc02
POWER-SUPPLY REJECTION vs. FREQUENCY
BW = 1kHz HOP = 5kHz
MAX3670 toc03
60
0 -10 SUPPLY REJECTION (dB) -20 -30 -40 -50 -60
SUPPLY CURRENT (mA)
50 3.3V 40
EDGE SPEED 20%-80% (ps)
5.0V
LOOP FILTER OUTPUT
622.08MHz
30
155.52MHz
20 -40 -20 0 20 40 60 80 TEMPERATURE (C)
-20
0
20
40
60
80
1k
10k
100k FREQUENCY (Hz)
1M
10M
TEMPERATURE (C)
622MHz CLOCK OUTPUT (DIFFERENTIAL OUTPUT)
MAX3670 toc04
155MHz CLOCK OUTPUT (DIFFERENTIAL OUTPUT)
MAX3670 toc05
200mV/ div
200mV/ div
500ps/div
2.0ns/div
_______________________________________________________________________________________
5
Low-Jitter 155MHz/622MHz Clock Generator MAX3670
Pin Description
PIN 1 2 3, 9, 15 4 5 6 7 8 10 11 12 13 14 16 17 18 19, 22 20 21 23 24 25 26 27 28 29 30 31 32 EP NAME C2+ C2VCCD THADJ CTH GSEL1 GSEL2 GSEL3 LOL GND RSEL REFCLK+ REFCLKVSEL POUTPOUT+ VCCO MOUTMOUT+ VCOINVCOIN+ VC POLAR PSEL1 PSEL2 VCCA COMP OPAMPOPAMP+ Exposed Pad FUNCTION Positive Filter Input. External capacitor connected between C2+ and C2- used for setting the higher-order pole frequency (see Setting the Higher-Order Poles). Negative Filter Input. External capacitor connected between C2+ and C2- used for setting the higherorder pole frequency (see Setting the Higher-Order Poles). Positive Digital Supply Voltage Threshold Adjust Input. Used to adjust the Loss-of-Lock threshold (see LOL Setup). Threshold Capacitor Input. A capacitor connected between CTH and ground used to control the Loss-ofLock conditions (see LOL Setup). Gain Select 1 Input. Three-level pin used to set the phase-detector gain (KPD) and the frequency-divider ratio (N2) (see Table 3). Gain Select 2 Input. Three-level pin used to set the phase-detector gain (KPD) and the frequency-divider ratio (N2) (see Table 3). Gain Select 3 Input. Three-level pin used to set the phase-detector gain (KPD) and the frequency-divider ratio (N2) (see Table 3). Loss-of-Lock. LOL signals a TTL low when the reference frequency differs from the VCO frequency. LOL signals a TTL high when the reference frequency equals the VCO frequency. Supply Ground Reference Clock Select Input. Three-level pin used to set the predivider ratio (N3) for the input reference clock (see Table 1). Positive Reference Clock Input Negative Reference Clock Input VCO Clock Select Input. Three-level pin used to set the predivider ratio (N1) for the input VCO clock (see Table 2). Negative Optional Clock Output, PECL Positive Optional Clock Output, PECL Positive Supply Voltage for PECL Outputs Negative Main Clock Output, PECL Positive Main Clock Output, PECL Negative VCO Clock Input Positive VCO Clock Input Control Voltage Output. The voltage output from the op amp that controls the VCO. Polarity Control Input. Polarity control of op amp input. POLAR = GND for VCOs with positive gain transfer. POLAR = VCC for VCOs with negative gain transfer. Optional Clock Select 1 Input. Used to set the divider ratio for the optional clock output (see Table 4). Optional Clock Select 2 Input. Used to set the divider ratio for the optional clock output (see Table 4). Positive Analog Supply Voltage for the Charge Pump and Op Amp Compensation Control Input. Op amp compensation reference control input. COMP = GND for VCOs whose control pin is VCC referenced. COMP = VCC for VCOs whose control pin is GND referenced. Negative Op Amp Input (POLAR = 0), Positive Op Amp Input (POLAR = 1) Positive Op Amp Input (POLAR = 0), Negative Op Amp Input (POLAR = 1) Ground. The exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance.
6
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
Functional Diagram
MAX3670
R3 VCO KVCO C3 LOL THADJ CTH VC COMP
C1
R1
C1 POLAR
R1 OPAMPOPAMP+
OPAMP LOL REFCLK+ REFCLKDIV (N3) DIV (N2) PFD/CP KPD C2-
RSEL VSEL DIV (N1) DIV (N2) PECL
C2+ MOUT+ MOUTPOUT+
VCOIN+ VCOIN-
GAIN-CONTROL LOGIC
MAX3670
DIV 1/2/4/8
PECL POUT-
GSEL1 GSEL2
GSEL3
PSEL1
PSEL2
Detailed Description
The MAX3670 contains all the blocks needed to form a PLL except for the VCO, which must be supplied separately. The MAX3670 consists of input buffers for the reference clock and VCO, input and output clock-divider circuitry, LOL detection circuitry, gain-control logic, a phase-frequency detector and charge pump, an op amp, and PECL output buffers. This device is designed to clean up the noise on the reference clock input and provide a low-jitter system clock output.
Input Buffer for Reference Clock and VCO
The MAX3670 contains differential inputs for the reference clock and the VCO. These inputs can be DC-coupled and are internally biased with high impedance so that they can be AC-coupled (Figure 1 in the Interface Schematic section). A single-ended VCO or reference clock can also be applied.
Input and Output Clock-Divider Circuitry
The reference clock and VCO input buffers are followed by a pair of clock dividers that prescale the input frequency of the reference clock and VCO to 77.76MHz.
7
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator MAX3670
Depending on the input clock frequency of 77.76MHz, 155.52MHz, or 622.08MHz, the clock divider ratio must be set to 1, 2, or 8, respectively. The POUT output buffer is preceded by a clock divider that scales the main clock output by 1, 2, 4, or 8 to provide an optional clock.
Table 1. Reference Clock Divider
INPUT PIN RSEL VCC OPEN GND REFERENCE CLOCK INPUT FREQ. (MHz) 77.76 155.52 622.08 DIVIDER RATIO N3 1 2 8 PREDIVIDER OUTPUT FREQ. (MHz) 77.76 77.76 77.76
LOL Detection Circuitry
The MAX3670 incorporates a loss-of-lock (LOL) monitor that consists of an XOR gate, filter, and comparator with adjustable threshold (see "LOL Setup" in the Applications section). A loss-of-lock condition is signaled with a TTL low when the reference clock frequency differs from the VCO frequency.
Gain-Control Logic
The gain-control circuitry facilitates the tuning of the loop bandwidth by setting phase-detector gain and frequency-divider ratio. The gain-control logic can be programmed to divide from 1 to 1024, in binary multiples, and to adjust the phase detector gain to 5A/UI or 20A/UI (see Table 3 in Setting the Loop Bandwidth section).
The MAX3670 is designed to accept 77.76MHz, 155.52MHz, or 622.08MHz (including FEC rates) voltage-controlled oscillator (VCO) frequencies. The VSEL input must be set so that the VCO input is prescaled to 77.76MHz (or FEC rate), to provide the proper range for the PFD and LOL detection circuitry. Table 2 shows the divider ratio for the different VCO frequencies.
Table 2. VCO Clock Divider
INPUT PIN VSEL VCC OPEN GND VCO CLOCK INPUT FREQ. (MHz) 77.76 155.52 622.08 DIVIDER RATIO N1 1 2 8 PREDIVIDER OUTPUT FREQ. (MHz) 77.76 77.76 77.76
Phase-Frequency Detector and Charge Pump
The phase-frequency detector incorporated into the MAX3670 produces pulses proportional to the phase difference between the reference clock and the VCO input. The charge pump converts this pulse train to a current signal that is fed to the op amp.
Setting the Loop Bandwidth
To eliminate jitter present on the reference clock, the proper selection of loop bandwidth is critical. If the total output jitter is dominated by the noise at the reference clock input, then lowering the loop bandwidth will reduce system jitter. The loop bandwidth (K) is a function of the VCO gain (KVCO), the gain of the phase detector (KPD), the loop filter resistor (R1), and the total feedback-divider ratio (N = N1 N2). The loop bandwidth of the MAX3670 can be approximated by K RK K = PD 1 VCO 2N For stability, a zero must be added to the loop in the form of resistor R1 in series with capacitor C1 (see Functional Diagram). The location of the zero can be approximated as fZ = 1 2R1C1
Op Amp
The op amp is used to form an active PLL loop filter capable of driving the VCO control voltage input. Using the POLAR input, the op amp input polarity can be selected to work with VCOs having positive or negative gaintransfer functions. The COMP pin selects the op amp internal compensation. Connect COMP to ground if the VCO control voltage is VCC referenced. Connect COMP to VCC if the VCO control voltage is ground referenced.
Design Procedure
Setting Up the VCO and Reference Clock
The MAX3670 accepts 77.76MHz, 155.52MHz, or 622.08MHz (including FEC rates) reference clock frequencies. The RSEL input must be set so that the reference clock is prescaled to 77.76MHz (or FEC rate), to provide the proper range for the PFD and LOL detection circuitry. Table 1 shows the divider ratio for the different reference frequencies.
Due to the second-order nature of the PLL jitter transfer, peaking will occur and is proportional to fZ/K. For certain applications, it may be desirable to limit jitter
8
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
Table 3. Gain Logic Pin Setup
INPUT PIN GSEL1 VCC OPEN GND VCC OPEN GND VCC OPEN GND VCC OPEN VCC OPEN GND VCC OPEN GND VCC OPEN GND VCC OPEN INPUT PIN GSEL2 VCC VCC VCC OPEN OPEN OPEN GND GND GND VCC VCC VCC VCC VCC OPEN OPEN OPEN GND GND GND OPEN OPEN INPUT PIN GSEL3 VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN GND GND KPD (A/UI) 20 20 20 20 20 20 20 20 20 20 20 5 5 5 5 5 5 5 5 5 5 5 DIVIDER RATIO N2 1 2 4 8 16 32 64 128 256 512 1024 1 2 4 8 16 32 64 128 256 512 1024
quency to be (K 4) < fHOP fCOMPARE, where K is the loop bandwidth. The HOP can be implemented either by providing a compensation capacitor C2, which produces a pole at f HOP = 1 2(20k)(C2 )
MAX3670
or by adding a lowpass filter, consisting of R3 and C3, directly on the VCO tuning port, which produces a pole at f HOP = 1 2R3C3
Using R3 and C3 may be preferable for filtering more noise in the PLL, but it may still be necessary to provide filtering via C2 when using large values of R1 and N1 N2 to prevent clipping in the op amp.
Setting the Optional Output
The MAX3670 optional clock output can be set to binary subdivisions of the main clock frequency. The PSEL1 and PSEL2 pins control the binary divisions. Table 4 shows the pin configuration along with the possible divider ratios.
Table 4. Setting the Optional Clock Output Driver
INPUT PIN PSEL1 VCC GND VCC GND INPUT PIN PSEL2 VCC VCC GND GND VCO TO POUT DIVIDER RATIO 1 2 4 8
peaking in the PLL passband region to less than 0.1dB. This can be achieved by setting fZ K/100. The three-level GSEL pins (see Functional Diagram) select the phase-detector gain (KPD) and the frequencydivider ratio (N2). Table 3 summarizes the settings for the GSEL pins. A more detailed analysis of the loop filter is located in application note HFDN-13.0 on www.maxim-ic.com.
Applications Information
PECL Interfacing
The MAX3670 outputs (MOUT+, MOUT-, POUT+, POUT-) are designed to interface with PECL signal levels. It is important to bias these ports appropriately. A circuit that provides a Thevenin equivalent of 50 to VCC - 2V can be used with fixed-impedance transmission lines with proper termination. To ensure best performance, the differential outputs must have balanced loads. It is important to note that if optional clock output is not used, it should be left floating to save power (see Figure 2).
Setting the Higher-Order Poles
Spurious noise is generated by the phase detector switching at the compare frequency, where fCOMPARE = fVCO/(N1 N2). Reduce the spurious noise from the digital phase detector by placing a higher-order pole (HOP) at a frequency much less than the compare frequency. The HOP should, however, be placed high enough in frequency that it does not decrease the overall loop-phase margin and impact jitter peaking. These two conditions can be met by selecting the HOP fre-
_______________________________________________________________________________________
9
Low-Jitter 155MHz/622MHz Clock Generator MAX3670
Layout
The MAX3670 performance can be significantly affected by circuit board layout and design. Use good highfrequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the reference and VCO clock signals. Power-supply decoupling should be placed as close to VCC pins as possible. Take care to isolate the input from the output signals to reduce feedthrough. quencies above the loop bandwidth may degrade LOL functionality. The user can set the amount of frequency or phase difference between VCO and reference clock at which LOL indicates an out-of-lock condition. The frequency difference is called the beat frequency. The CTH pin can be connected to an external capacitor, which sets the lowpass filter frequency to approximately f L= 1 2CTH 60k
VCO Selection
The MAX3670 is designed to accommodate a wide range of VCO gains, positive or negative transfer slopes, and VCC-referenced or ground-referenced control voltages. These features allow the user a wide range of options in VCO selection; however, the proper VCO must be selected to allow the clock generator circuitry to operate at the optimum levels. When selecting a VCO, the user needs to take into account the phase noise and modulation bandwidth. Phase noise is important because the phase noise above the PLL bandwidth will be dominated by the VCO noise performance. The modulation bandwidth of the VCO contributes an additional higher-order pole (HOP) to the system and should be greater than the HOP set with the external filter components.
This lowpass filter frequency should be set about 10 times lower than the beat frequency to make sure the filtered signal at CTH does not drop below the THADJ threshold voltage. The internal compare frequency of the part is 77.78MHz. For a 1ppm sensitivity (beat frequency of 77Hz), the filter needs to be at 7.7Hz, and CTH should be at 0.33F. The voltage at THADJ will determine the level at which the LOL output flags. THADJ is set to a default value of 0.6V which corresponds in a 45 phase difference. This value can be overridden by applying the desired threshold voltage to the pin. The range of THADJ is from 0V (0) to 2.4V (180).
Noise Performance Optimization
Depending on the application, there are many different ways to optimize the PLL performance. The following are general guidelines to improve the noise on the system output clock. 1) If the reference clock noise dominates the total system-clock output jitter, then decreasing the loop bandwidth (K) reduces the output jitter. 2) If the VCO noise dominates the total system clock output jitter, then increasing the loop bandwidth (K) reduces the output jitter. 3) Smaller total divider ratio (N1 N2), lower HOP, and smaller R1 reduce the spurious output jitter. 4) Smaller R1 reduces the random noise due to the op amp.
REFLCK+
Interface Schematics
VCC
VCC - 1.3V
10.5k
10.5k
LOL Setup
The LOL output indicates if the PLL has locked onto the reference clock using an XOR gate and comparator. The comparator threshold can be adjusted with THADJ, and the XOR gate output can be filtered with a capacitor between CTH and ground (Figure 3 in the Interface Schematic section). When the voltage at pin CTH exceeds the voltage at pin THADJ, then the LOL output goes low and indicates that the PLL is not locked. Note that excessive jitter on the reference clock input at freREFLCK-
MAX3670
Figure 1. Input Interface
10
______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
Interface Schematics (continued)
VCC LOL
MAX3670
60k OUT+ OUT0.6V
THADJ
CTH 60k REFCLK MAX3670 VCO MAX3670
Figure 2. Output Interface
Figure 3. Loss-of-Lock Indicator
Pin Configuration
OPAMP+ OPAMPVCCA POLAR COMP PSEL2 PSEL1
Chip Information
TRANSISTOR COUNT: 2478
32 C2+ C2VCCD THADJ CTH GSEL1 GSEL2 GSEL3 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25 24 23 22 21 VCOIN+ VCOINVCCO MOUT+ MOUTVCCO POUT+ POUT-
MAX3670*
VC
20 19 18 17 16
10
11
12
13
14
15
REFCLK+
RSEL
REFCLK-
VCCD
*THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND.
______________________________________________________________________________________
VCCD
VSEL
GND
LOL
11
Low-Jitter 155MHz/622MHz Clock Generator MAX3670
Package Information
12
______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
Package Information (continued)
MAX3670
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX3670

	To Download MAX3670 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .